STK6054

The STK6054 is an 8-bit micro-controller. It consists of a 1T 8051 core, a 16K byte internal program Flash
ROM, support hardware ISP/IAP function, 1024-byte SRAM, max. 23 I/O pins (for SSOP28), three 16-bit
timer/counter, (Timer 0,1,2), two UART serial ports, 13 interrupt sources, a watchdog timer, and a 8-channel 10 bits
A/D converter. 12-channel PWM, SPI master/slave mode and IIC master/slave mode, 5 channels of PCA.

Product Features
-8-bit 1T 8051 micro-controller
-Operating voltage: 2.7V – 5.5V
-Three clock sources: Internal HRC with 5.5MHz frequency (default), internal LRC with 32KHz frequency, and
XTAL (2 ~ 25MHz)
-768-bytes SRAM + MCU internal 256byte RAM
-16K bytes program Flash ROM
-23 bi-directional IO pins (max.)
- NLDO with LVR and POR
-12-channel PWM with adjustable frequency and 4 setting of bit-depth 4, 6, 8, 10 bit
-Three programmable 16-bit timers or counters (Timer0/1/2)
-Built-in watch-dog-timer
-Two full-duplex serial ports (UART0/UART1)
-Hardware SPI interface that could work as master or slave
-5 channels of PCA (16 bit Timer0/Timer1/capture mode/HSO/16bit PWM/8bit PWM functions)
-Hardware code protection
-Enhanced the noise immunity capability for crystal pads
-13 interrupt sources
- Power consumption under 1mA at idle mode
-Power consumption under 15uA at sleep mode
-Hardware ISP (In-System Programming) / IAP (In-Application Programming) function
- -40°C ~ +85°C working range
- EFT ≥ 4KV
-ESD test ≥ 4KV without system reset
- Package designed with SOP28, SOP20, DIP20, and DIP16

STK6031

FEATURES
• 80C51 Central Processing Unit (CPU).
– Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1/3 ).
– Industrial standard 80C51 instruction set.
– Normal mode, idle mode, and stop mode.
• Program Memory : 64 kbytes on-chip flash memory.
– with hardware ISP (In-System Programming).
– Program code protection.
• Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.
• Aux Memory (AUX RAM): 768 bytes of SRAM.
• Stretch memory cycle for the MOVX instruction.
• SFRs (Special Function Register): 47 SFRs.
• Timers: Timer 0, Timer 1, and Timer 2.
• On-chip Watchdog Timer.
• Full-duplex UART
• Five I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4 (P4.0 ~ P4.3).
• On-chip power-on-reset with low-voltage detection and reset.
• Interrupts: 6 sources, 2 priority level, 6 vectored addresses.
• Software enable/disable of ALE output pulse to reduce EMI.
• 4-channel, 6-bit ADC.
• 5-channel, 8-bit PWM.
• CPU operating frequency range: 2 to 30 MHz
• Operating temperature range: -20 to +85°C
• Operating voltage range: 2.7 to 3.6 V.
• ESD: ≥3 KV (HBM).
• Latch-up: 150 mA.
• Relibility of 64K flash memory:
– Data retention: 10 years at room temperature.
– Number of read/write cycle: > 20K.
• Available in 3 types of Pb-free package: PLCC44, QFP44, LQFP48

STK6032

FEATURES
• 80C51 Central Processing Unit (CPU).
– Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1/3.
– Binary-code compatible with industrial standard 80C51 instruction set.
– Normal mode, idle mode, and stop mode.
• Program Memory : 64 kbytes on-chip flash memory.
– with hardware ISP (In-System Programming).
– Program code protection.
• Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.
• Aux Memory (AUX RAM): 768 bytes of SRAM.
• Stretched memory cycle for the MOVX instruction.
• SFRs (Special Function Register): 46 SFRs.
• Timers: Timer 0, Timer 1, and Timer 2.
• On-chip Watchdog Timer.
• Full-duplex UART
• Five 8-bits I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4.
• On-chip power-on-reset with low-voltage detection and reset.
• Interrupts: 6 sources, 2 priority level, 6 vectored addresses.
• Software enable/disable of ALE output pulse to reduce EMI.
• 6-channel, 6-bit ADC.
• 5-channel, 8-bit PWM.
• CPU operating frequency range: 2 to 30 MHz
• Operating temperature range: -40 to +85°C
• Operating voltage range: 4.5 to 5.5 V.
• ESD, Human Body Model: > 3 KV
• ESD, Machines model: > 350 V
• Latch-up > 100 mA.
• Relibility of 64K flash memory:
– Data retention: 10 years at room temperature.
– Number of read/write cycle: > 20K.
• Available in 3 types of Pb-free package: PLCC44, QFP44, LQFP48.

STK6033

FEATURES
• 80C51 Central Processing Unit (CPU).
– Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1/3 ).
– Industrial standard 80C51 instruction set.
– Normal mode, idle mode, and stop mode.
• Program Memory : 16 kbytes on-chip flash memory.
– with hardware ISP (In-System Programming).
– Program code protection.
• Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.
• Aux Memory (AUX RAM): 320 bytes of SRAM.
• Stretch memory cycle for the MOVX instruction.
• SFRs (Special Function Register): 51 SFRs.
• Timers: Timer 0, Timer 1, and Timer 2.
• On-chip Watchdog Timer.
• Full-duplex UART
• Five 8-bit I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4.
• On-chip power-on-reset with low-voltage detection and reset.
• Interrupts: 6 sources, 2 priority level, 6 vectored addresses.
• Software enable/disable of ALE output pulse to reduce EMI.
• 6-channel, 10-bit ADC.
• 5-channel, 8-bit PWM.
• CPU operating frequency range: 2 to 30 MHz
• Operating temperature range: -40 to +85°C
• Operating voltage range: 4.2 to 5.6 V.
• ESD: ≥4 KV (HBM).
• Latch-up: 150 mA.
• Relibility of 16K flash memory:
– Data retention: 10 years at room temperature.
– Number of read/write cycle: > 20K.
• Available in 5 types of green package: PLCC44, QFP44, LQFP48, DIP40, and SOP20